load and register-to-memory store i

load and register-to-memory store instructions. Note that many of the instructions
use a three-operand format. Also, many instructions have a number of variants,
depending on the location of the operands. A source operand may be a vector
register (V), storage (S), or a scalar register (Q). The target is always a vector
register, except for comparison, the result of which goes into the vector-mask
register. With all these variants, the total number of opcodes (distinct instructions)
is 171. This rather large number, however, is not as expensive to implement as might
be imagined. Once the machine provides the arithmetic units and the data paths
to feed operands from storage, scalar registers, and vector registers to the vector
pipelines, the major hardware cost has been incurred. The architecture can, with
little difference in cost, provide a rich set of variants on the use of those registers
and pipelines.