Pipeline Hazards
In the previous subsection, we mentioned some of the situations that can result in
less than optimal pipeline performance. In this subsection, we examine this issue in
a more systematic way. Chapter 14 revisits this issue, in more detail, after we have introduced the complexities found in superscalar pipeline organizations.
A pipeline hazardoccurs when the pipeline, or some portion of the pipeline,
must stall because conditions do not permit continued execution. Such a pipeline
stall is also referred to as a pipeline bubble. There are three types of hazards:
resource, data, and control.
RESOURCE HAZARDSA resource hazard occurs when two (or more) instructions
that are already in the pipeline need the same resource. The result is that the instructions must be executed in serial rather than parallel for a portion of the
pipeline. A resource hazard is sometime referred to as a structural hazard.
Let us consider a simple example of a resource hazard.Assume a simplified fivestage pipeline, in which each stage takes one clock cycle. Figure 12.15a shows the ideal case, in which a new instruction enters the pipeline each clock cycle. Now assume that
main memory has a single port and that all instruction fetches and data reads and
writes must be performed one at a time. Further, ignore the cache. In this case, an
operand read to or write from memory cannot be performed in parallel with an in
struction fetch. This is illustrated in Figure 12.15b, which assumes that the source
operand for instruction I1 is in memory, rather than a register. Therefore, the fetch in
struction stage of the pipeline must idle for one cycle before beginning the instruction
fetch for instruction I3. The figure assumes that all other operands are in registers.
Another example of a resource conflict is a situation in which multiple in
structions are ready to enter the execute instruction phase and there is a single
ALU. One solutions to such resource hazards is to increase available resources, such
as having multiple ports into main memory and multiple ALU units.
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