• The amount of cache memory that i

• The amount of cache memory that is shared
Figure 18.8 shows four general organizations for multicore systems. Figure
18.8a is an organization found in some of the earlier multicore computer chips and
is still seen in embedded chips. In this organization, the only on-chip cache is L1
cache, with each core having its own dedicated L1 cache. Almost invariably, the L1
cache is divided into instruction and data caches. An example of this organization is
the ARM11 MPCore.
The organization of Figure 18.8b is also one in which there is no on-chip cache
sharing. In this, there is enough area available on the chip to allow for L2 cache.
An example of this organization is the AMD Opteron. Figure 18.8c shows a similar
allocation of chip space to memory, but with the use of a shared L2 cache. The Intel
Core Duo has this organization. Finally, as the amount of cache memory available
on the chip continues to grow, performance considerations dictate splitting off a
separate, shared L3 cache, with dedicated L1 and L2 caches for each core processor.
The Intel Core i7 is an example of this organization.
The use of a shared L2 cache on the chip has several advantages over exclusive
reliance on dedicated caches:
1. Constructive interference can reduce overall miss rates. That is, if a thread on
one core accesses a main memory location, this brings the frame containing
the referenced location into the shared cache. If a thread on another core soon
thereafter accesses the same memory block, the memory locations will already
be available in the shared on-chip cache.
2. A related advantage is that data shared by multiple cores is not replicated at
the shared cache level.
3. With proper frame replacement algorithms, the amount of shared cache allo-
cated to each core is dynamic, so that threads that have a less locality can
employ more cache.