W(i)  Write to line by processor i

W(i)  Write to line by processor i
R(i)  Read line by processor i
Z(i)  Displace line by cache i
W( j)  Write to line by processor j ( j fi i)
R( j)  Read line by processor j ( j fi i)
Z( j)  Displace line by cache j ( j fi i)
Note: State diagrams are for a
given line in cache i
Z( j )
Z(i)
Z(i)
Figure 17.22 Two Cache Coherence Protocols
3. P1 writes to x (label the line in P1’s cache x
).
4. P2 reads x.
17.5 Figure 17.22 shows the state diagrams of two possible cache coherence protocols.
Deduce and explain each protocol, and compare each to MESI.
17.6 Consider an SMP with both L1 and L2 caches using the MESI protocol. As explained
in Section 17.3, one of four states is associated with each line in the L2 cache. Are all
four states also needed for each line in the L1 cache? If so, why? If not, explain which
state or states can be eliminated.
17.7 An earlier version of the IBM mainframe, the S/390 G4, used three levels of cache.
As with the z990, only the first level was on the processor chip [called the processor
unit (PU)]. The L2 cache was also similar to the z990. An L3 cache was on a separate
chip that acted as a memory controller, and was interposed between the L2 caches
and the memory cards. Table 17.4 shows the performance of a three-level cache arrangement
for the IBM S/390. The purpose of this problem is to determine whether
the inclusion of the third level of cache seems worthwhile. Determine the access
penalty (average number of PU cycles) for a system with only an L1 cache, and normalize
that value to 1.0. Then determine the normalized access penalty when both
an L1 and L2 cache are used, and the access penalty when all three caches are used.
Note the amount of improvement in each case and state your opinion on the value
of the L3 cache.
17.8 a. Consider a uniprocessor with separate data and instruction caches, with hit ratios
of Hd and Hi, respectively. Access time from processor to cache is c clock cycles,
and transfer time for a block between memory and cache is b clock cycles. Let fi