August 1986Revised April 2000DM74LS

August 1986
Revised April 2000
DM74LS123
Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
Features
The DM74LS123 is a dual retriggerable monostable multi-
vibrator capable of generating output pulses from a few
nano-seconds to extremely long duration up to 100% duty
cycle. Each device has three inputs permitting the choice of
either leading edge or trailing edge triggering. Pin (A) is an
active-LOW transition trigger input and pin (B) is an active-
HIGH transition trigger input. The clear (CLR) input termi-
nates the output pulse at a predetermined time indepen-
dent of the timing components. The clear input also serves
as a trigger input when it is pulsed with a low level pulse
transition ( ). To obtain the best trouble free operation
from this device please read the operating rules as well as
the Fairchild Semiconductor one-shot application notes
carefully and observe recommendations.
■ DC triggered from active-HIGH transition or active-LOW
transition inputs
■ Retriggerable to 100% duty cycle
■ Compensated for VCC
and temperature variations
■ Triggerable from CLEAR input
■ DTL, TTL compatible
■ Input clamp diodes
Ordering Code:
Order Number
DM74LS123M
DM74LS123SJ
DM74LS123N
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M16D
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Outputs
CLEAR
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↑
↑
↓
H
H
L
H  HIGH Logic Level
L  LOW Logic Level
X  Can Be Either LOW or HIGH
↑ Positive Going Transition
↓ Negative Going Transition
 A Positive Pulse
 A Negative Pulse
© 2000 Fairchild Semiconductor Corporation
DS006386
www.fairchildsemi.com




Functional Description
The basic output pulse width is determined by selection of
an external resistor (RX) and capacitor (CX). Once trig-
gered, the basic pulse width may be extended by retrigger-
ing the gated active-LOW transition or active-HIGH
transition inputs or be reduced by use of the active-LOW or
CLEAR input. Retriggering to 100% duty cycle is possible
by application of an input pulse train whose cycle time is
shorter than the output cycle time such that a continuous
“HIGH” logic state is maintained at the “Q” output.
Operating Rules
1.
An external resistor (RX) and an external capacitor (CX)
are required for proper operation. The value of CX may
vary from 0 to any necessary value. For small time con-
stants high-grade mica, glass, polypropylene, polycar-
bonate, or polystyrene material capacitors may be
used. For large time constants use tantalum or special
aluminum capacitors. If the timing capacitors have
leakages approaching 100 nA or if stray capacitance
from either terminal to ground is greater than 50 pF the
timing equations may not represent the pulse width the
device generates.
2.
When an electrolytic capacitor is used for C X a switch-
ing diode is often required for standard TTL one-shots
to prevent high inverse leakage current. This switching
diode is not needed for the DM74LS123 one-shot and
should not be used. In general the use of the switching
diode is not recommended with retriggerable operation.
FIGURE 2.
5.
For CX 1000 pF see Figure 3 for tW vs. CX
family
curves with RX as a parameter:
Furthermore, if a polarized timing capacitor is used on
the DM74LS123 the negative terminal of the capacitor
should be connected to the “CEXT” pin of the device
(Figure 1).
FIGURE 3.
6.
To obtain variable pulse widths by remote trimming, the
following circuit is recommended:
FIGURE 1.
For CX 1000 pF the output pulse width (tW) is
defined as follows:
3.
tW  KRX CX
where [RX is in kΩ]
[CX is in pF]
FIGURE 4.
[tW
is in ns]
“Rremote
” should be as close to the device pin as possible.
K ≈ 0.37
7.
The retriggerable pulse width is calculated as shown
below:
4.
The multiplicative factor K is plotted as a function of CX
below for design considerations:
T  tW  tPLH  K  RX  CX  tPLH
The retriggered pulse width is equal to the pulse width
plus a delay time period (Figure 5).
FIGURE 5.
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2




Operating Rules
(Continued)
8.
Output pulse width variation versus V CC
tures: Figure 6 depicts the relationship between pulse
width variation versus VCC
width variation versus temperatures.
and tempera-
9.
Under any operating condition CX and RX must be kept
as close to the one-shot device pins as possible to min-
imize stray capacitance, to reduce noise pick-up, and
to reduce I-R and Ldi/dt voltage developed along their
connecting paths. If the lead length from C X to pins (6)
, and Figure 7 depicts pulse
and (7) or pins (14) and (15) is greater than 3 cm, for
example, the output pulse width might be quite different
from values predicted from the appropriate equations.
A non-inductive and low capacitive path is necessary to
ensure complete discharge of CX in each cycle of its
operation so that the output pulse width will be accu-
rate.
10. The CEXT
pins of this device are internally connected to
the internal ground. For optimum system performance
they should be hard wired to the system’s return
ground plane.
11. VCC and ground wiring should conform to good high-
frequency standards and practices so that switching
transients on the VCC and ground return leads do not
FIGURE 6.
cause interaction between one-shots. A 0.01 F to 0.10
F bypass capacitor (disk ceramic or monolithic type)
from VCC
thermore, the bypass capacitor should be located as
close to the VCC
to ground is necessary on each device. Fur-
-pin as space permits.
Note: For further detailed device characteristics and output per-
formance please refer to the Fairchild Semiconductor one-shot
application note AN-372.
FIGURE 7.
3
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Absolute Maximum Ratings
(Note 1)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Supply Voltage
7V
7V
Input Voltage
Operating Free Air Temperature Range
0C to 70C
−65C to 150C
Storage Temperature
Recommended Operating Conditions
Symbol
Parameter
Min
4.75
2
Nom
Max
Units
V
VCC
Supply Voltage
5
5.25
VIH
VIL
IOH
IOL
tW
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Pulse Width
V
0.8
−0.4
8
V
mA
mA
A or B HIGH
A or B LOW
Clear LOW
40
40
40
5
(Note 2)
ns
REXT
CEXT
CWIRE
TA
External Timing Resistor
260
kΩ
F
pF
C
External Timing Capacitance
No Restriction
Wiring Capacitance at REXT/CEXT
Terminal
50
70
Free Air Operating Temperature
0
Note 2: TA  25C and VCC  5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 3)
VI
VOH
Input Clamp Voltage
VCC Min, II −18 mA
VCC Min, IOH  Max
VIL Max, VIH  Min
VCC Min, IOL  Max
VIL Max, VIH  Min
IOL 4 mA, VCC  Min
VCC Max, VI  7V
−1.5
V
V
HIGH Level
2.7
3.4
Output Voltage
LOW Level
VOL
0.35
0.25
0.5
Output Voltage
V
0.4
0.1
II
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
mA
A
IIH
IIL
IOS
ICC
VCC Max, VI  2.7V
VCC Max, VI  0.4V
VCC Max (Note 4)
20
−0.4
−100
20
mA
mA
mA
−20
VCC Max (Note 5)(Note 6)(Note 7)
12
Note 3: All typicals are at VCC  5V, TA  25C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs OPEN, CEXT  0.02 F,
and REXT  25 kΩ.
Note 6: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs OPEN, CEXT  0.02 F,
and REXT  25 kΩ.
Note 7: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC
is measured after a momentary ground, then 4.5V is applied to the clock.
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4




Switching Characteristics
at VCC  5V and TA 25C
RL 2 kΩ
From (Input)
To (Output)
CL  15pF
CEXT 0 pF, REXT 5 kΩ
CL  15pF
Symbol
Parameters
Units
CEXT 1000 pF, REXT 10 kΩ
Min
Max
Min
Max
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
A to Q
B to Q
33
ns
ns
tPLH
tPHL
tPHL
44
45
56
Propagation Delay Time
A to Q
B to Q
ns
ns
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Minimum Width of Pulse
at Output Q
Clear to Q
Clear to Q
45
27
ns
ns
tPHL
tWQ(Min)
A or B to Q
A or B to Q
200
ns
tW(out)
Output Pulse Width
4
5
s
5
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Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com
6




Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
www.fairchildsemi.com




Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP),

Kết quả (Việt) 1:

Tháng tám 1986Sửa đổi tháng 4 năm 2000DM74LS123Kép Retriggerable thêm với kết quả đầu ra rõ ràng và bổ sungMô tả chungTính năngDM74LS123 là một đa kép retriggerable monostable-rung khả năng tạo ra sản lượng xung từ một vàiNano-giây để thời gian rất dài lên đến 100% các nhiệm vụchu kỳ. Mỗi thiết bị có ba đầu vào cho phép lựa chọnhoặc là cạnh hàng đầu hoặc đuôi kích hoạt. Pin (A) là mộtquá trình chuyển đổi hoạt động-thấp kích hoạt đầu vào và pin (B) là một hoạt động-Các đầu vào kích hoạt quá trình chuyển đổi cao. Rõ ràng (CLR) nhập termi-nates đầu ra xung tại một thời gian định trước indepen-Dent thành thời gian. Đầu rõ ràng cũng phục vụnhư là một kích hoạt đầu vào khi nó pulsed với một xung thấp cấpchuyển đổi (). Để có được các hoạt động rắc rối miễn phí tốt nhấttừ thiết bị này xin vui lòng đọc các điều hành quy tắc cũng nhưFairchild Semiconductor one-shot ứng dụng notesmột cách cẩn thận và quan sát khuyến nghị.■ DC kích hoạt từ quá trình chuyển đổi cao hoạt động hoặc hoạt động-thấpđầu vào quá trình chuyển đổi■ Retriggerable với chu kỳ nhiệm vụ 100%■ đền bù cho VCC và nhiệt độ biến thể■ Triggerable từ rõ ràng đầu vào■ DTL, TTL tương thích■ Nhập kẹp điốtĐặt hàng mã:Số đơn đặt hàngDM74LS123MDM74LS123SJDM74LS123NGói sốM16AMô tả gói16-chì phác thảo nhỏ mạch tích hợp (SOIC), JEDEC MS-012, 0.150 hẹp16-chì phác thảo nhỏ gói (SOP), EIAJ loại II, 5,3 mm rộng16-lead nhựa kép trong dòng gói (PDIP), JEDEC MS-001, 0.300 WideM16DN16EDevices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Connection DiagramFunction TableInputsOutputsCLEARAXHXLBXXLQLLLQHHHLXXHH↑↑↓HHLH  HIGH Logic LevelL  LOW Logic LevelX  Can Be Either LOW or HIGH↑ Positive Going Transition↓ Negative Going Transition A Positive Pulse A Negative Pulse© 2000 Fairchild Semiconductor CorporationDS006386www.fairchildsemi.com Functional DescriptionThe basic output pulse width is determined by selection ofan external resistor (RX) and capacitor (CX). Once trig-gered, the basic pulse width may be extended by retrigger-ing the gated active-LOW transition or active-HIGHtransition inputs or be reduced by use of the active-LOW orCLEAR input. Retriggering to 100% duty cycle is possibleby application of an input pulse train whose cycle time isshorter than the output cycle time such that a continuous“HIGH” logic state is maintained at the “Q” output.Operating Rules1.An external resistor (RX) and an external capacitor (CX)are required for proper operation. The value of CX mayvary from 0 to any necessary value. For small time con-stants high-grade mica, glass, polypropylene, polycar-bonate, or polystyrene material capacitors may beused. For large time constants use tantalum or specialaluminum capacitors. If the timing capacitors haveleakages approaching 100 nA or if stray capacitancefrom either terminal to ground is greater than 50 pF thetiming equations may not represent the pulse width thedevice generates.2.When an electrolytic capacitor is used for C X a switch-ing diode is often required for standard TTL one-shotsto prevent high inverse leakage current. This switchingdiode is not needed for the DM74LS123 one-shot andshould not be used. In general the use of the switchingdiode is not recommended with retriggerable operation.FIGURE 2. 5.For CX 1000 pF see Figure 3 for tW vs. CXfamilycurves with RX as a parameter:Furthermore, if a polarized timing capacitor is used onthe DM74LS123 the negative terminal of the capacitorshould be connected to the “CEXT” pin of the device(Figure 1).FIGURE 3. 6.To obtain variable pulse widths by remote trimming, thefollowing circuit is recommended:FIGURE 1. For CX 1000 pF the output pulse width (tW) isdefined as follows:3.tW  KRX CXwhere [RX is in kΩ][CX is in pF]FIGURE 4. [tW is in ns]“Rremote” should be as close to the device pin as possible.K ≈ 0.377.The retriggerable pulse width is calculated as shownbelow:4.The multiplicative factor K is plotted as a function of CXbelow for design considerations:T  tW  tPLH  K  RX  CX  tPLHThe retriggered pulse width is equal to the pulse widthplus a delay time period (Figure 5).FIGURE 5. www.fairchildsemi.com2 Operating Rules (Continued)8.Output pulse width variation versus V CCtures: Figure 6 depicts the relationship between pulsewidth variation versus VCCwidth variation versus temperatures. and tempera-9.Under any operating condition CX and RX must be keptas close to the one-shot device pins as possible to min-imize stray capacitance, to reduce noise pick-up, andto reduce I-R and Ldi/dt voltage developed along theirconnecting paths. If the lead length from C X to pins (6), and Figure 7 depicts pulseand (7) or pins (14) and (15) is greater than 3 cm, forexample, the output pulse width might be quite differentfrom values predicted from the appropriate equations.A non-inductive and low capacitive path is necessary toensure complete discharge of CX in each cycle of itsoperation so that the output pulse width will be accu-rate.10. The CEXT pins of this device are internally connected tothe internal ground. For optimum system performancethey should be hard wired to the system’s returnground plane.11. VCC and ground wiring should conform to good high-frequency standards and practices so that switchingtransients on the VCC and ground return leads do notFIGURE 6. cause interaction between one-shots. A 0.01 F to 0.10F bypass capacitor (disk ceramic or monolithic type)from VCCthermore, the bypass capacitor should be located asclose to the VCC to ground is necessary on each device. Fur--pin as space permits.Note: For further detailed device characteristics and output per-formance please refer to the Fairchild Semiconductor one-shotapplication note AN-372.FIGURE 7. 3www.fairchildsemi.com Absolute Maximum Ratings(Note 1)Note 1: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditionsfor actual device operation.Supply Voltage7V7VInput VoltageOperating Free Air Temperature Range0C to 70C−65C to 150CStorage TemperatureRecommended Operating ConditionsSymbolParameterMin4.752NomMaxUnitsVVCCSupply Voltage55.25VIHVILIOHIOLtWHIGH Level Input VoltageLOW Level Input VoltageHIGH Level Output CurrentLOW Level Output CurrentPulse WidthV0.8−0.48VmAmAA or B HIGHA or B LOWClear LOW4040405(Note 2)nsREXTCEXTCWIRETAExternal Timing Resistor260kΩFpFCExternal Timing CapacitanceNo RestrictionWiring Capacitance at REXT/CEXT Terminal5070Free Air Operating Temperature0Note 2: TA  25C and VCC  5V.Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)TypSymbolParameterConditionsMinMaxUnits(Note 3)VIVOHInput Clamp VoltageVCC Min, II −18 mA
VCC Min, IOH  Max
VIL Max, VIH  Min
VCC Min, IOL  Max
VIL Max, VIH  Min
IOL 4 mA, VCC  Min
VCC Max, VI  7V
−1.5
V
V
HIGH Level
2.7
3.4
Output Voltage
LOW Level
VOL
0.35
0.25
0.5
Output Voltage
V
0.4
0.1
II
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
mA
A
IIH
IIL
IOS
ICC
VCC Max, VI  2.7V
VCC Max, VI  0.4V
VCC Max (Note 4)
20
−0.4
−100
20
mA
mA
mA
−20
VCC Max (Note 5)(Note 6)(Note 7)
12
Note 3: All typicals are at VCC  5V, TA  25C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: Quiescent ICC is measured (after clearing) with 2.4V applied to all clear and A inputs, B inputs grounded, all outputs OPEN, CEXT  0.02 F,
and REXT  25 kΩ.
Note 6: ICC is measured in the triggered state with 2.4V applied to all clear and B inputs, A inputs grounded, all outputs OPEN, CEXT  0.02 F,
and REXT  25 kΩ.
Note 7: With all outputs OPEN and 4.5V applied to all data and clear inputs, ICC
is measured after a momentary ground, then 4.5V is applied to the clock.
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4




Switching Characteristics
at VCC  5V and TA 25C
RL 2 kΩ
From (Input)
To (Output)
CL  15pF
CEXT 0 pF, REXT 5 kΩ
CL  15pF
Symbol
Parameters
Units
CEXT 1000 pF, REXT 10 kΩ
Min
Max
Min
Max
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
A to Q
B to Q
33
ns
ns
tPLH
tPHL
tPHL
44
45
56
Propagation Delay Time
A to Q
B to Q
ns
ns
HIGH-to-LOW Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
tPLH
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Minimum Width of Pulse
at Output Q
Clear to Q
Clear to Q
45
27
ns
ns
tPHL
tWQ(Min)
A or B to Q
A or B to Q
200
ns
tW(out)
Output Pulse Width
4
5
s
5
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Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com
6




Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
www.fairchildsemi.com




Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP),