2. Select additional blocks of mark

2. Select additional blocks of marked squares that are as large as possible and
as few in number as possible, but include every marked square at least once.
The results may not be unique in some cases. For example, if a marked square
combines with exactly two other squares, and there is no fourth marked square
to complete a larger group, then there is a choice to be made as two which of
the two groupings to choose. When you are circling groups, you are allowed to
use the same 1 value more than once.
3. Continue to draw loops around single marked squares, or pairs of adjacent
marked squares, or groups of four, eight, and so on in such a way that every
marked square belongs to at least one loop; then use as few of these blocks as
possible to include all marked squares.
Figure 11.9a, based on Table 11.3, illustrates the simplification process. If any
isolated 1s remain after the groupings, then each of these is circled as a group of 1s.
Finally, before going from the map to a simplified Boolean expression, any group of
1s that is completely overlapped by other groups can be eliminated. This is shown in
Figure 11.9b. In this case, the horizontal group is redundant and may be ignored in
creating the Boolean expression.
One additional feature of Karnaugh maps needs to be mentioned. In some
cases, certain combinations of values of variables never occur, and therefore the
corresponding output never occurs. These are referred to as “don’t care” conditions.
For each such condition, the letter “d” is entered into the corresponding
square of the map. In doing the grouping and simplification, each “d” can be treated
as a 1 or 0, whichever leads to the simplest expression.
An example, presented in [HAYE98], illustrates the points we have been discussing.
We would like to develop the Boolean expressions for a circuit that adds
1 to a packed decimal digit. For packed decimal, each decimal digit is represented
by a 4-bit code, in the obvious way. Thus, 0 = 0000, 1 = 0001, c, 8 = 1000, and
9 = 1001. The remaining 4-bit values, from 1010 to 1111, are not used. This code is
also referred to as Binary Coded Decimal (BCD).
Table 11.4 shows the truth table for producing a 4-bit result that is one
more than a 4-bit BCD input. The addition is modulo 10. Thus, 9 + 1 = 0. Also,
note that six of the input codes produce “don’t care” results, because those are
not valid BCD inputs. Figure 11.10 shows the resulting Karnaugh maps for each
of the output variables. The d squares are used to achieve the best possible
groupings.
THE QUINE–MCCLUSKEY METHOD For more than four variables, the Karnaugh
map method becomes increasingly cumbersome. With five variables, two 16 * 16
maps are needed, with one map considered to be on top of the other in three
dimensions to achieve adjacency. Six variables require the use of four 16 * 16
tables in four dimensions! An alternative approach is a tabular technique, referred
to as the Quine–McCluskey method. The method is suitable for programming on a
computer to give an automatic tool for producing minimized Boolean expressions.
The method is best explained by means of an example. Consider the following
expression:
ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CD
Let us assume that this expression was derived from a truth table. We would
like to produce a minimal expression suitable for implementation with gates.
The first step is to construct a table in which each row corresponds to one
of the product terms of the expression. The terms are grouped according to the
number of complemented variables. That is, we start with the term with no complements,
if it exists, then all terms with one complement, and so on. Table 11.5 shows
the list for our example expression, with horizontal lines used to indicate the grouping.
For clarity, each term is represented by a 1 for each uncomplemented variable
and a 0 for each complemented variable. Thus, we group terms according to the
number of 1s they contain. The index column is simply the decimal equivalent and
is useful in what follows.
The next step is to find all pairs of terms that differ in only one variable, that is,
all pairs of terms that are the same except that one variable is 0 in one of the terms
and 1 in the other. Because of the way in which we have grouped the terms, we can
do this by starting with the first group and comparing each term of the first group
with every term of the second group. Then compare each term of the second group
with all of the terms of the third group, and so on. Whenever a match is found, place
a check next to each term, combine the pair by eliminating the variable that differs
in the two terms, and add that to a new list. Thus, for example, the terms ABCD and
ABCD are combined to produce ABC. This process continues until the entire original
table has been examined. The result is a new table with the following entries:
A CD ABC ABD 
BCD ACD
ABC BCD 
ABD
Table 11.5 First Stage of Quine–McCluskey Method
(for F = ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CD)
The new table is organized into groups, as indicated, in the same fashion as the
first table. The second table is then processed in the same manner as the first. That is,
terms that differ in only one variable are checked and a new term produced for a third
table. In this example, the third table that is produced contains only one term: BD.
In general, the process would proceed through successive tables until a table
with no matches was produced. In this case, this has involved three tables.
Once the process just described is completed, we have eliminated many of
the possible terms of the expression. Those terms that have not been eliminated
are used to construct a matrix, as illustrated in Table 11.6. Each row of the matrix
corresponds to one of the terms that have not been eliminated (has no check) in
any of the tables used so far. Each column corresponds to one of the terms in the
original expression. An X is placed at each intersection of a row and a column such
that the row element is “compatible” with the column element. That is, the variables
present in the row element have the same value as the variables present in the
column element. Next, circle each X that is alone in a column. Then place a square
around each X in any row in which there is a circled X. If every column now has
either a squared or a circled X, then we are done, and those row elements whose
Xs have been marked constitute the minimal expression. Thus, in our example, the
final expression is
ABC + ACD + ABC + A CD
In cases in which some columns have neither a circle nor a square, additional
processing is required. Essentially, we keep adding row elements until all columns
are covered.
Let us summarize the Quine–McCluskey method to try to justify intuitively
why it works. The first phase of the operation is reasonably straightforward. The
process eliminates unneeded variables in product terms. Thus, the expression
ABC + ABC is equivalent to AB, because
ABC + ABC = AB(C + C) = AB
After the elimination of variables, we are left with an expression that is clearly
equivalent to the original expression. However, there may be redundant terms
in this expression, just as we found redundant groupings in Karnaugh maps. The
matrix layout assures that each term in the original expression is covered and does
so in a way that minimizes the number of terms in the final expression.
Table 11.6 Last Stage of Quine–McCluskey Method
(for F = ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CD)
NAND AND NOR IMPLEMENTATIONS Another consideration in the
implementation of Boolean functions concerns the types of gates used. It is sometimes
desirable to implement a Boolean function solely with NAND gates or solely with
NOR gates. Although this may not be the minimum-gate implementation, it has the
advantage of regularity, which can simplify the manufacturing process. Consider
again Equation (11.3):
F = B(A + C)
Because the complement of the complement of a value is just the original value,
F = B(A + C) = (AB + (BC)
Applying DeMorgan’s theorem,
F = (AB)•(BC)
which has three NAND forms, as illustrated in Figure 11.11.
Multiplexers
The multiplexer connects multiple inputs to a single output. At any time, one of the
inputs is selected to be passed to the output. A general block diagram representation
is shown in Figure 11.12. This represents a 4-to-1 multiplexer. There are four input
lines, labeled D0, D1, D2, and D3. One of these lines is selected to provide the
A
B
B
C
F
Figure 11.11 NAND Implementation of
output signal F. To select one of the four possible inputs, a 2-bit selection code is
needed, and this is implemented as two select lines labeled S1 and S2.
An example 4-to-1 multiplexer is defined by the truth table in Table 11.7. This
is a simplified form of a truth table. Instead of showing all possible combinations of
input variables, it shows the output as data from line D0, D1, D2, or D3. Figure 11.13
shows an implementation using AND, OR, and NOT gates. S1 and S2 are connected
to the AND gates in such a way that, for any combination of S1 and S2, three of the
AND gates will output 0. The fourth AND gate will output the value of the selected
line, which is either 0 or 1. Thus, three of the inputs to the OR gate are always 0,
and the output of the OR gate will equal the value of the selected input gate. Using
this regular organization, it is easy to construct multiplexers of size 8-to-1, 16-to-1,
and so on.
Multiplexers are used in digital circuits to control signal and data routing. An
example is the loading of the program counter (PC). The value to be loaded into the
program counter may come from one of several different sources:
• A binary counter, if the PC is to be incremented for the next instruction
• The instruction register, if a branch instruction using a direct address has just
been executed
• The output of the ALU, if the branch instruction specifies the address using a

Kết quả (Việt) 1:

2. chọn bổ sung khối của hình vuông được đánh dấu là lớn nhất có thể vàsố tại càng ít càng tốt, nhưng bao gồm mỗi hình vuông được đánh dấu ít nhất một lần.Kết quả có thể không phải là duy nhất trong một số trường hợp. Ví dụ, nếu một hình vuông được đánh dấukết hợp với chính xác hai ô vuông khác, và không có quảng trường được đánh dấu thứ tưđể hoàn thành một nhóm lớn hơn, sau đó có một sự lựa chọn được thực hiện là hai trong sốhai nhóm để lựa chọn. Khi bạn xoay quanh nhóm, bạn được phépsử dụng cùng một giá trị 1 nhiều hơn một lần.3. tiếp tục để vẽ vòng quanh duy nhất hình vuông được đánh dấu, hoặc cặp liền kềđánh dấu ô vuông, hoặc nhóm của bốn, tám, và như vậy trong một cách mà mỗiđánh dấu square thuộc ít nhất một vòng lặp; sau đó sử dụng như là vài trong số các khối nhưcó thể bao gồm đánh dấu tất cả các hình vuông.Con số 11.9a, dựa trên bảng 11.3, minh hoạ đơn giản hóa quá trình. Nếu bất kỳbị cô lập 1s vẫn còn sau khi nhóm, sau đó mỗi trong số này được bao quanh là một nhóm 1s.Cuối cùng, trước khi đi từ bản đồ một biểu thức Boolean đơn giản, bất kỳ nhóm nào của1s mà hoàn toàn chồng chéo bởi các nhóm khác có thể được loại bỏ. Điều này được thể hiện trongCon số 11.9b. Trong trường hợp này, nhóm ngang là dư thừa và có thể được bỏ qua trongviệc tạo ra các biểu thức Boolean.Một tính năng bổ sung của Karnaugh bản đồ cần phải được đề cập. Trong một sốtrường hợp, một số kết hợp của các giá trị của các biến không bao giờ xảy ra, và do đó cácđầu ra tương ứng không bao giờ xảy ra. Đây được gọi là "không quan tâm" điều kiện.Cho mỗi điều kiện như vậy, chữ "d" được nhập vào tương ứnghình vuông của bản đồ. Bằng cách nhóm và đơn giản hóa, mỗi "d" có thể được điều trịnhư 1 hoặc 0, tùy theo cái nào dẫn đến biểu thức đơn giản nhất.Ví dụ, trình bày trong [HAYE98], minh họa các điểm chúng tôi đã thảo luận.Chúng tôi mong muốn phát triển các biểu thức Boolean đối với một vi mạch cho biết thêm rằng1 để một chữ số thập phân đóng gói. Đối với bữa thập phân, mỗi chữ số thập phân được đại diệntheo một mã 4-bit, trong cách rõ ràng. Vì vậy, 0 = 0000, 1 = 0001, c, 8 = 1000, và9 = 1001. Giá trị 4-bit còn lại, từ 1010 đến 1111, không được sử dụng. Mã này làcũng được gọi là nhị phân mã hóa thập phân (BCD).Cho thấy bảng 11,4 để sản xuất một kết quả 4-bit là một bảng chân trịnhiều hơn một BCD 4-bit đầu vào. Việc bổ sung là theo modulo 10. Vì vậy, 9 + 1 = 0. Ngoài ra,lưu ý rằng sáu mã đầu vào sản xuất kết quả "không quan tâm", bởi vì đó làkhông hợp lệ BCD đầu vào. Con số 11,10 cho thấy các kết quả Karnaugh bản đồ cho mỗicủa biến đầu ra. Các ô vuông d được sử dụng để đạt được tốt nhất có thểNhóm.Các QUINE-MCCLUSKEY phương pháp cho nhiều hơn bốn biến, Karnaughbản đồ phương pháp trở nên ngày càng rườm rà. Với năm biến, hai 16 * 16bản đồ là cần thiết, với một bản đồ được coi là trên đầu trang của nhau trong baKích thước để đạt được kề. Sáu biến yêu cầu việc sử dụng bốn 16 * 16bảng trong không gian bốn chiều! Một cách tiếp cận khác là một kỹ thuật bảng, được gọito as the Quine–McCluskey method. The method is suitable for programming on acomputer to give an automatic tool for producing minimized Boolean expressions.The method is best explained by means of an example. Consider the followingexpression:ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CDLet us assume that this expression was derived from a truth table. We wouldlike to produce a minimal expression suitable for implementation with gates.The first step is to construct a table in which each row corresponds to oneof the product terms of the expression. The terms are grouped according to thenumber of complemented variables. That is, we start with the term with no complements,if it exists, then all terms with one complement, and so on. Table 11.5 showsthe list for our example expression, with horizontal lines used to indicate the grouping.For clarity, each term is represented by a 1 for each uncomplemented variableand a 0 for each complemented variable. Thus, we group terms according to thenumber of 1s they contain. The index column is simply the decimal equivalent andis useful in what follows.The next step is to find all pairs of terms that differ in only one variable, that is,all pairs of terms that are the same except that one variable is 0 in one of the termsand 1 in the other. Because of the way in which we have grouped the terms, we cando this by starting with the first group and comparing each term of the first groupwith every term of the second group. Then compare each term of the second groupwith all of the terms of the third group, and so on. Whenever a match is found, placea check next to each term, combine the pair by eliminating the variable that differsin the two terms, and add that to a new list. Thus, for example, the terms ABCD andABCD are combined to produce ABC. This process continues until the entire originaltable has been examined. The result is a new table with the following entries:A CD ABC ABD BCD ACDABC BCD ABDTable 11.5 First Stage of Quine–McCluskey Method(for F = ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CD)The new table is organized into groups, as indicated, in the same fashion as thefirst table. The second table is then processed in the same manner as the first. That is,terms that differ in only one variable are checked and a new term produced for a thirdtable. In this example, the third table that is produced contains only one term: BD.In general, the process would proceed through successive tables until a tablewith no matches was produced. In this case, this has involved three tables.Once the process just described is completed, we have eliminated many ofthe possible terms of the expression. Those terms that have not been eliminatedare used to construct a matrix, as illustrated in Table 11.6. Each row of the matrixcorresponds to one of the terms that have not been eliminated (has no check) inany of the tables used so far. Each column corresponds to one of the terms in the
original expression. An X is placed at each intersection of a row and a column such
that the row element is “compatible” with the column element. That is, the variables
present in the row element have the same value as the variables present in the
column element. Next, circle each X that is alone in a column. Then place a square
around each X in any row in which there is a circled X. If every column now has
either a squared or a circled X, then we are done, and those row elements whose
Xs have been marked constitute the minimal expression. Thus, in our example, the
final expression is
ABC + ACD + ABC + A CD
In cases in which some columns have neither a circle nor a square, additional
processing is required. Essentially, we keep adding row elements until all columns
are covered.
Let us summarize the Quine–McCluskey method to try to justify intuitively
why it works. The first phase of the operation is reasonably straightforward. The
process eliminates unneeded variables in product terms. Thus, the expression
ABC + ABC is equivalent to AB, because
ABC + ABC = AB(C + C) = AB
After the elimination of variables, we are left with an expression that is clearly
equivalent to the original expression. However, there may be redundant terms
in this expression, just as we found redundant groupings in Karnaugh maps. The
matrix layout assures that each term in the original expression is covered and does
so in a way that minimizes the number of terms in the final expression.
Table 11.6 Last Stage of Quine–McCluskey Method
(for F = ABCD + ABCD + ABC D + ABCD + ABCD + ABCD + ABCD + A B CD)
NAND AND NOR IMPLEMENTATIONS Another consideration in the
implementation of Boolean functions concerns the types of gates used. It is sometimes
desirable to implement a Boolean function solely with NAND gates or solely with
NOR gates. Although this may not be the minimum-gate implementation, it has the
advantage of regularity, which can simplify the manufacturing process. Consider
again Equation (11.3):
F = B(A + C)
Because the complement of the complement of a value is just the original value,
F = B(A + C) = (AB + (BC)
Applying DeMorgan’s theorem,
F = (AB)•(BC)
which has three NAND forms, as illustrated in Figure 11.11.
Multiplexers
The multiplexer connects multiple inputs to a single output. At any time, one of the
inputs is selected to be passed to the output. A general block diagram representation
is shown in Figure 11.12. This represents a 4-to-1 multiplexer. There are four input
lines, labeled D0, D1, D2, and D3. One of these lines is selected to provide the
A
B
B
C
F
Figure 11.11 NAND Implementation of
output signal F. To select one of the four possible inputs, a 2-bit selection code is
needed, and this is implemented as two select lines labeled S1 and S2.
An example 4-to-1 multiplexer is defined by the truth table in Table 11.7. This
is a simplified form of a truth table. Instead of showing all possible combinations of
input variables, it shows the output as data from line D0, D1, D2, or D3. Figure 11.13
shows an implementation using AND, OR, and NOT gates. S1 and S2 are connected
to the AND gates in such a way that, for any combination of S1 and S2, three of the
AND gates will output 0. The fourth AND gate will output the value of the selected
line, which is either 0 or 1. Thus, three of the inputs to the OR gate are always 0,
and the output of the OR gate will equal the value of the selected input gate. Using
this regular organization, it is easy to construct multiplexers of size 8-to-1, 16-to-1,
and so on.
Multiplexers are used in digital circuits to control signal and data routing. An
example is the loading of the program counter (PC). The value to be loaded into the
program counter may come from one of several different sources:
• A binary counter, if the PC is to be incremented for the next instruction
• The instruction register, if a branch instruction using a direct address has just
been executed
• The output of the ALU, if the branch instruction specifies the address using a