Most PCs are held back not by the s

Most PCs are held back not by the speed of their main processor, but by the time it takes to move data in and out of memory. One of the most important techniques for getting around this bottleneck is the memory cache.
The idea is to use a small number of very fast memory chips as a buffer or cache between main memory and the processor. Whenever the processor needs to read data it looks in this cache area first. If it finds the data in the cache then this counts as a 'cache hit' and the processor need not go through the more laborious process of reading data from the main memory. Only if the data is not in the cache does it need to access main memory, but in the process it copies whatever it finds into the cache so that it is there ready for the next time it is needed. The whole process is controlled by a group of logic circuits called the cache controller.
One of the cache controller's main jobs is to look after 'cache coherency' which means ensuring that any changes written to main memory are reflected within the cache and vice versa. There are several techniques for achieving this, the most obvious being for the processor to write directly to both the cache and main memory at the same time. This is known as a 'write-through' cache and is the safest solution, but also the slowest.
The main alternative is the 'write-back' cache which allows the processor to write changes only to the cache and not to main memory. Cache entries that have changed are flagged as 'dirty' telling the cache controller to write their contents back to main memory before using the space to cache new data. A write-back cache speeds up the write process, but does require a more intelligent cache controller.
Most cache controllers move a 'line' of data rather than just a single item each time they need to transfer data between main memory and the cache. This tends to improve the chance of a cache hit as most programs spend their time stepping through instructions stored sequentially in memory, rather than jumping about from one area to another. The amount of data transferred each time is known as the 'line size'.

Kết quả (Java) 1:

Paling PC sing dianakaké bali ora dening kacepetan prosesor sing utama, nanging wektu iku njupuk kanggo mindhah data ing lan metu saka memori. Salah Techniques paling penting kanggo njupuk sak purwakanthi iki cache memori.
idea iku kanggo nggunakake nomer cilik Kripik memori cepet banget minangka buffer utawa cache antarane memori utama lan prosesor. Kapan prosesor perlu kanggo maca data katon ing wilayah cache iki pisanan. Yen ketemu data ing cache banjur iki counts minangka 'cache hit' lan prosesor ora perlu mbukak liwat proses luwih laborious maca data saka memori utama. Mung yen data ora ana ing cache ora perlu ngakses memori utama, nanging ing iku salinan proses punapa mawon ketemu menyang cache supaya iku ana siap kanggo sabanjuré wektu iku perlu. Proses wutuh wis kontrol dening klompok sirkuit logika disebut controller cache.
Salah proyek utama cache controller iku kanggo katon sawise 'cache jaman' kang tegese njupuk sing owah-owahan ditulis kanggo memori utama sing dibayangke ing cache lan kosok balene. Ana sawetara Techniques kanggo nampa iki, kang paling ketok kanggo prosesor kanggo nulis langsung menyang loro cache lan memori utama ing wektu sing padha. Iki dikenal minangka 'nulis-liwat' cache lan solusi safest, nanging uga slowest.
Alternatif utama iku 'nulis-bali' cache sing ngijini prosesor kanggo nulis owahan mung kanggo mbusak singgahan lan ora memori utama. Èntri '' cache sing wis diganti sing gendero minangka 'reged' nuduhake kontrol cache kanggo nulis isi sing bali menyang memori utama sadurunge nggunakake papan kanggo ngakses data anyar. Kecepatan A cache nulis-bali nganti proses nulis, nanging ora mbutuhake cache controller liyane cerdas.
Paling pengontrol cache mindhah 'baris' data tinimbang mung item siji saben wektu padha kudu ngirim data antarane memori utama lan papan singgahan. Iki cenderung kanggo nambah kasempatan saka hit cache minangka sing paling program nglampahi wektu sing mlaku liwat instruksi sequentially disimpen ing memori, tinimbang jumping babagan saka siji wilayah liyane. Jumlah data sing ditransfer saben wektu iki dikenal minangka 'ukuran baris.